SID Oscillator Verilog Fun

The past few days I’ve been waiting for Pokey synth front panel circuit boards to come in, so I thought I’d play around with some “soundchip” Verilog. Kevtris has already done a SID emulation in an FPGA (and understands the internals of the SID far better than I do), but I haven’t seen any code posted. I saw this blog post and eventually ended up at this interview I bookmarked a year or so ago.

I wrote some Verilog strictly according to the interview, specifically making an oscillator with triangle, saw, pulse, and noise outputs. I added in the logic “AND” of the triangle and saw waves as an additional waveform, according to Bob Yannes’ comments about multiple waveforms being selected at once. Here’s what the digital outputs looks like:

Only the Waviest

Only the Waviest

My source code is available here. I included excerpts from the interview as comments because it just felt so right. Open it with Notepad++ for best results (if you want all the formatting to line up properly).

What I still need to figure out:

The interview mentions that the LFSR for noise generation is clocked by one of the accumulator bits. Which bit is it?

Another excerpt from the interview that I’m partially unclear about: “The combination was actually a logical ANDing of the bits of each waveform, which produced unpredictable results, so I didn’t encourage this, especially since it could lock up the pseudo-random sequence generator by filling it with zeroes.” A linear feedback shift register shouldn’t be able to get filled with all zeros on its own.┬áThis implies that the LFSR shift register does not take feedback taps from itself, but actually taps somewhere further down the line (after the logical AND). Is it actually feeding back from the Waveform D/A input bits? In that case, what happens to the LFSR while it isn’t selected as a waveform?

Are the inputs to the Waveform D/A registered synchronously to the master clock, or do glitches pop up from not having every bit change at exactly the same time?

At this point I really need to fire up an actual SID to start checking my assumptions, but I’m afraid that if I touch a SID now then I’ll end up too distracted when the Pokey synth prototype PCBs come in.

2 Responses to “SID Oscillator Verilog Fun”

  1. Deon Formey says:

    Thanks this is very informative . Already bookmarked your website