Skrasoft Dev Blog

The past few days I’ve been waiting for Pokey synth front panel circuit boards to come in, so I thought I’d play around with some “soundchip” Verilog. Kevtris has already done a SID emulation in an FPGA (and understands the internals of the SID far better than I do), but I haven’t seen any code posted. I saw this blog post and eventually ended up at this interview I bookmarked a year or so ago.

I wrote some Verilog strictly according to the interview, specifically making an oscillator with triangle, saw, pulse, and noise outputs. I added in the logic “AND” of the triangle and saw waves as an additional waveform, according to Bob Yannes’ comments about multiple waveforms being selected at once. Here’s what the digital outputs looks like:

Only the Waviest

My source code is available here. I included excerpts from the interview as comments because it just felt so right. Open it with Notepad++ for best results (if you want all the formatting to line up properly).

What I still need to figure out:

The interview mentions that the LFSR for noise generation is clocked by one of the accumulator bits. Which bit is it?

Another excerpt from the interview that I’m partially unclear about: “The combination was actually a logical ANDing of the bits of each waveform, which produced unpredictable results, so I didn’t encourage this, especially since it could lock up the pseudo-random sequence generator by filling it with zeroes.” A linear feedback shift register shouldn’t be able to get filled with all zeros on its own. This implies that the LFSR shift register does not take feedback taps from itself, but actually taps somewhere further down the line (after the logical AND). Is it actually feeding back from the Waveform D/A input bits? In that case, what happens to the LFSR while it isn’t selected as a waveform?

Are the inputs to the Waveform D/A registered synchronously to the master clock, or do glitches pop up from not having every bit change at exactly the same time?

At this point I really need to fire up an actual SID to start checking my assumptions, but I’m afraid that if I touch a SID now then I’ll end up too distracted when the Pokey synth prototype PCBs come in.

Most of my hobby time lately has been spent sourcing parts and doing circuit layout for the Pokey module, but yesterday I spent a little more time with the 1-bit D/A I was working on. Spectral plots are in order!

Running the output of the FPGA directly into my soundcard with a couple wires, this is the output spectrum for a 1k sine wave:

Blue Picket Fences

Alright, so that looks pretty terrible. The sine wave data is 16-bit, so the noise floor should be around -96 dB (the bottom line of the graph), yet it’s in the -86 range. There’s also a lot of distortion: both even and odd harmonics.

One potential reason for these problems is that my soundcard probably does not like 25 MHz input frequencies. To help that a little bit, I added an RC filter between the FPGA and soundcard. Using 16 kHz as a cutoff, the new result looks like this:

Noise Censorship

That’s much better. True CD quality would just have one spike at 1000 (for 1 kHz), as 2k, 3k, 4k… are distortions. The worst case offender is just under -40dB, giving this converter noise performance greater than 16-bit, but distortion performance that’s around 7-bit. I do not have an obvious solution for the distortion problem, nor can I prove with my current setup that it *isn’t* just a result of my soundcard not being able to handle the high frequency energy. If anyone has any insights, please add a comment or two.