I need to find a better way to record video. An iPhone camera doesn’t do justice to the 70 frames per second of the screen.
This was a weekend project proof-of-concept for a low budget FPGA GPU. To be fair, it took a couple nights beforehand to get the display configured to recognize an RGB interface. That configuration is handled by a PIC at the moment.
The FPGA design is made of several engines running in parallel:
1) Background grid generator
2) Audio data plotter (including a UART receiver for getting data from a computer)
3) Geometry engines (one per shape)
4) Parallel RGB interface (this drives the LCD)
To keep the memory requirements tiny, there is no frame buffering of any kind for the geometry engines. The RGB interface steps through each pixel on the screen and passes the current coordinate location data to the other engines. Each engine returns a 1 (pixel on) or 0 (pixel off). The last step is a mixing block that defines the color and depth for the output of each engine. For example, the lowest layer is the background grid. Next up is the circle, and so on up to the audio plot. Only the highest illuminated pixel is shown for each location on the screen.
The geometry engines store the size and locations of their shapes in registers, so the only memory usage comes from the audio data drawn on top of everything. Audio data is being generated by Max/MSP and sent over a USB > serial cable. The FPGA double buffers it so that there aren’t any glitches due to synchronization issues.
A major downside to this general approach is that the amount of logic scales proportionally to the number of objects on the screen. If there are going to be 5 circles on the screen, this design needs 5 circle generators. One way to improve that is to use a faster clock in geometry calculations. Then each engine could handle multiple shapes per pixel.
Long-term goals: thick lines, anti-aliasing, sprites, and text rendering.
The display is 320 * 240 pixels running at 70 fps. The complete design as shown uses 415 logic elements, 8192 bits of memory, and three 9-bit multipliers (for circle calculations). For a reference, the smallest Altera Cyclone IV FPGA has 6272 logic elements, 270 kbit of memory, and thirty 9-bit multipliers.